Tradeoffs in Delay Guarantees and Computation Complexity for Packet Switches

We consider the tradeoffs between packet delay guarantees and per-timeslot computation complexity in an packet switch operating under the crossbar constraint. It is well known that scheduling packets every timeslot according to a Maximum Weight Matching (MWM) achieves 100% throughput. This algorithm ensures average packet delay is within O(n) timeslots (where n is the number of input ports of the switch) but is quite complex to implement, requiring O(n3) computations every slot to compute the schedule. Here we develop a modified version of MWM which reduces computation complexity while still ensuring 100% throughput and offering polynomial delay bounds. Specifically, we develop a class of scheduling policies (parameterized by ) which achieve a per-timeslot computation complexity of O(nα) and ensure O(n4-α) bounds on average delay. In particular, linear per-timeslot computation complexity is achievable with an O(n3) delay guarantee (case α=1). Furthermore, as , complexity can be made as low as desired while delay is held within O(n4). These results for the first time illustrate an explicit tradeoff between performance and scheduling complexity.